SCL2Start Counting High PeriodInternal Counter ResetSCL1SCLDelayFigure 36-3. I2C clock synchronization36.5.1.8 HandshakingThe clock synchronization mechanism can be used as a handshake in data transfers. Aslave device may hold SCL low after completing a single byte transfer (9 bits). In thiscase, it halts the bus clock and forces the master clock into wait states until the slavereleases SCL.36.5.1.9 Clock stretchingThe clock synchronization mechanism can be used by slaves to slow down the bit rate ofa transfer. After the master drives SCL low, a slave can drive SCL low for the requiredperiod and then release it. If the slave's SCL low period is greater than the master's SCLlow period, the resulting SCL bus signal's low period is stretched. In other words, theSCL bus signal's low period is increased to be the same length as the slave's SCL lowperiod.36.5.1.10 I2C divider and hold valuesNOTEFor some cases on some devices, the SCL divider value mayvary by ±2 or ±4 when ICR's value ranges from 00h to 0Fh.These potentially varying SCL divider values are highlighted inthe following table. For the actual SCL divider values for yourdevice, see the chip-specific details about the I2C module.Chapter 36 Inter-Integrated Circuit (I2C)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 631
