23.6.1.2 Pseudo-code exampleIn this example, the ADC module is set up with interrupts enabled to perform a single 10-bit conversion at low-power with a long sample time on input channel 1, where ADCK isderived from the bus clock divided by 1.CFG1 = 0x98 (%10011000)Bit 7 ADLPC 1 Configures for low power, lowers maximum clock speed.Bit 6:5 ADIV 00 Sets the ADCK to the input clock ÷ 1.Bit 4 ADLSMP 1 Configures for long sample time.Bit 3:2 MODE 10 Selects the single-ended 10-bit conversion, differential 11-bit conversion.Bit 1:0 ADICLK 00 Selects the bus clock.SC2 = 0x00 (%00000000)Bit 7 ADACT 0 Flag indicates if a conversion is in progress.Bit 6 ADTRG 0 Software trigger selected.Bit 5 ACFE 0 Compare function disabled.Bit 4 ACFGT 0 Not used in this example.Bit 3 ACREN 0 Compare range disabled.Bit 2 DMAEN 0 DMA request disabled.Bit 1:0 REFSEL 00 Selects default voltage reference pin pair (External pinsVREFH and VREFL).SC1A = 0x41 (%01000001)Bit 7 COCO 0 Read-only flag which is set when a conversion completes.Bit 6 AIEN 1 Conversion complete interrupt enabled.Bit 5 DIFF 0 Single-ended conversion selected.Bit 4:0 ADCH 00001 Input channel 1 selected as ADC input channel.RA = 0xxxHolds results of conversion.CV = 0xxxHolds compare value when compare function enabled.Initialization informationKL27 Sub-Family Reference Manual , Rev. 5, 01/2016382 Freescale Semiconductor, Inc.
