Table 7-2. Module operation in low power modes (continued)Modules VLPR VLPW Stop VLPS LLS VLLSxUART2 62.5 kbit/sstatic, wakeupon edge in CPO62.5 kbit/s static, wakeupon edgeFF in PSTOP2static, wakeupon edgestatic OFFSPI0 (withoutFIFO)master mode500 kbit/s,slave mode 250kbit/sstatic, slavemode receive inCPOmaster mode500 kbit/s,slave mode 250kbit/sstatic, slavemode receiveFF in PSTOP2static, slavemode receivestatic OFFSPI1 (with FIFO) master mode 2Mbit/s,slave mode 1Mbit/sstatic, slavemode receive inCPOmaster mode 2Mbit/s,slave mode 1Mbit/sstatic, slavemode receivestatic, slavemode receivestatic OFFI2C0 100 kbit/sstatic, addressmatch wakeupin CPO100 kbit/s static, addressmatch wakeupstatic, addressmatch wakeupstatic OFFI2C1 100 kbit/sstatic, addressmatch wakeupin CPO100 kbit/s static, addressmatch wakeupstatic, addressmatch wakeupstatic OFFI2S FFAsync operationin CPOFF Async operationFF in PSTOP2Async operation static OFFFlexIO FF FF FF FF static OFFTimersTPM FFAsync operationin CPOFF Async operationFF in PSTOP2Async operation static OFFPIT FFstatic in CPOFF static static static OFFLPTMR FF FF Async operationFF in PSTOP2Async operation Async operation Asyncoperation4RTC FFAsync operationin CPOFF Async operationFF in PSTOP2Async operation Async operation Asyncoperation5Analog16-bit ADC FF FF ADC internalclock onlyFF in PSTOP2ADC internalclock onlystatic OFFTable continues on the next page...Module operation in low-power modesKL27 Sub-Family Reference Manual , Rev. 5, 01/201698 Freescale Semiconductor, Inc.
