SPIx_C2 = 0xC0(%11000000)Bit 3 BIDIROE = 0 SPI data I/O pin acts as inputBit 2 RXDMAE = 0 DMA request disabledBit 1 SPISWAI = 0 SPI clocks operate in wait modeBit 0 SPC0 = 0 uses separate pins for data input and outputSPIx_BR = 0x00(%00000000)Bit 7 = 0 ReservedBit 6:4 = 000 Sets prescale divisor to 1Bit 3:0 = 0000 Sets baud rate divisor to 2SPIx_S = 0x00(%00000000)Bit 7 SPRF = 0 Flag is set when receive data buffer is fullBit 6 SPMF = 0 Flag is set when SPIx_MH/ML = receive data bufferBit 5 SPTEF = 0 Flag is set when transmit data buffer is emptyBit 4 MODF = 0 Mode fault flag for master modeBit 3:0 RNFULLF,TNEARF,TXFULLF, andRFIFOEF= 0 Reserved (when FIFOMODE is not present or is 0) or FIFOflags (when FIFOMODE is 1)Bit 3:0 = 0 FIFOMODE is not enabledSPIx_MH = 0xXXIn 16-bit mode, this register holds bits 8–15 of the hardware match buffer. In 8-bit mode, writes to this registerwill be ignored.SPIx_ML = 0xXXHolds bits 0–7 of the hardware match buffer.SPIx_DH = 0xxxIn 16-bit mode, this register holds bits 8–15 of the data to be transmitted by the transmit buffer and received bythe receive buffer.SPIx_DL = 0xxxHolds bits 0–7 of the data to be transmitted by the transmit buffer and received by the receive buffer.Chapter 35 Serial Peripheral Interface (SPI)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 607
