The following figure shows how the execution trace information is stored in memory as asequence of packets.IncrementingSRAM memoryaddressNth destination addressNth source addressSA31 012nd destination address2nd source addressSA31 011st destination address1st source addressSAAtom bitStart bitOdd word addressEven word addressOdd word addressEven word addressFigure 43-2. MTB execution trace storage formatThe first, lower addressed, word contains the source of the branch, the address itbranched from. The value stored only records bits[31:1] of the source address, becauseThumb instructions are at least halfword aligned. The least significant bit of the value isthe A-bit. The A-bit indicates the atomic state of the processor at the time of the branch,and can differentiate whether the branch originated from an instruction in a program, anexception, or a PC update in Debug state. When it is zero the branch originated from aninstruction, when it is one the branch originated from an exception or PC update inDebug state. This word is always stored at an even word location.The second, higher addressed word contains the destination of the branch, the address itbranched to. The value stored only records bits[31:1] of the branch address. The leastsignificant bit of the value is the S-bit. The S-bit indicates where the trace started. An S-bit value of 1 indicates where the first packet after the trace started and a value of 0 isused for other packets. Because it is possible to start and stop tracing multiple times in atrace session, the memory might contain several packets with the S-bit set to 1. This wordis always stored in the next higher word in memory, an odd word address.When the A-bit is set to 1, the source address field contains the architecturally-preferredreturn address for the exception. For example, if an exception was caused by an SVCinstruction, then the source address field contains the address of the following instruction.This is different from the case where the A-bit is set to 0. In this case, the source addresscontains the address of the branch instruction.For an exception return operation, two packets are generated:• The first packet has the:• Source address field set to the address of the instruction that causes the exceptionreturn, BX or POP.Chapter 43 Micro Trace Buffer (MTB)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 853
