23.5.4.5 Sample time and total conversion timeFor short sample, that is, when CFG1[ADLSMP]=0, there is a 2-cycle adder for firstconversion over the base sample time of four ADCK cycles. For high-speed conversions,that is, when CFG2[ADHSC]=1, there is an additional 2-cycle adder on any conversion.The table below summarizes sample times for the possible ADC configurations.ADC configuration Sample time (ADCK cycles)CFG1[ADLSMP] CFG2[ADLSTS] CFG2[ADHSC] First or Single Subsequent0 X 0 6 41 00 0 241 01 0 161 10 0 101 11 0 60 X 1 8 61 00 1 261 01 1 181 10 1 121 11 1 8The total conversion time depends upon:• The sample time as determined by CFG1[ADLSMP] and CFG2[ADLSTS]• The MCU bus frequency• The conversion mode, as determined by CFG1[MODE] and SC1n[DIFF]• The high-speed configuration, that is, CFG2[ADHSC]• The frequency of the conversion clock, that is, fADCK.CFG2[ADHSC] is used to configure a higher clock input frequency. This will allowfaster overall conversion times. To meet internal ADC timing requirements,CFG2[ADHSC] adds additional ADCK cycles. Conversions with CFG2[ADHSC]=1 taketwo more ADCK cycles. CFG2[ADHSC] must be used when the ADCLK exceeds thelimit for CFG2[ADHSC]=0.After the module becomes active, sampling of the input begins.1. CFG1[ADLSMP] and CFG2[ADLSTS] select between sample times based on theconversion mode that is selected.2. When sampling is completed, the converter is isolated from the input channel and asuccessive approximation algorithm is applied to determine the digital value of theanalog signal.3. The result of the conversion is transferred to Rn upon completion of the conversionalgorithm.Chapter 23 Analog-to-Digital Converter (ADC)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 369
