NOTEWhen the FIFO is not supported or not enabled (FIFOMODE isnot present or is 0): Bits 3 through 0 are not implemented andalways read 0.When the FIFO is supported and enabled (FIFOMODE is 1): This register has four flagsthat provide mechanisms to support an 8-byte FIFO mode: RNFULLF, TNEARF,TXFULLF, and RFIFOEF. When the SPI is in 8-byte FIFO mode, the function of SPRFand SPTEF differs slightly from their function in the normal buffered modes, mainlyregarding how these flags are cleared by the amount available in the transmit and receiveFIFOs.• The RNFULLF and TNEAREF help improve the efficiency of FIFO operation whentransfering large amounts of data. These flags provide a "watermark" feature of theFIFOs to allow continuous transmissions of data when running at high speed.• The RNFULLF can generate an interrupt if the RNFULLIEN bit in the C3 register isset, which allows the CPU to start emptying the receive FIFO without delaying thereception of subsequent bytes. The user can also determine if all data in the receiveFIFO has been read by monitoring the RFIFOEF.• The TNEAREF can generate an interrupt if the TNEARIEN bit in the C3 register isset, which allows the CPU to start filling the transmit FIFO before it is empty andthus to prevent breaks in SPI transmission.NOTEAt an initial POR, the values of TNEAREF and RFIFOEF are0. However, the status (S) register and both TX and RX FIFOsare reset due to a change of SPIMODE, FIFOMODE or SPE. Ifthis type of reset occurs and FIFOMODE is 0, TNEAREF andRFIFOEF continue to reset to 0. If this type of reset occurs andFIFOMODE is 1, TNEAREF and RFIFOEF reset to 1.Address: Base address + 0h offsetBit 7 6 5 4 3 2 1 0Read SPRF SPMF SPTEF MODF RNFULLF TNEAREF TXFULLF RFIFOEFWrite w1cReset 0 0 1 0 0 0 0 0SPIx_S field descriptionsField Description7SPRFSPI Read Buffer Full Flag (when FIFO is not supported or not enabled) or SPI read FIFO FULL flag (whenFIFO is supported and enabled)When the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): SPRF is set at thecompletion of an SPI transfer to indicate that received data may be read from the SPI data (DH:DL)register. When the receive DMA request is disabled (RXDMAE is 0), SPRF is cleared by reading SPRFwhile it is set and then reading the SPI data register. When the receive DMA request is enabled (RXDMAETable continues on the next page...Chapter 35 Serial Peripheral Interface (SPI)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 575
