SIM_CLKDIV1 field descriptionsField Description31–28OUTDIV1Clock 1 Output Divider valueSets the divide value for the core/system clock, as well as the bus/flash clocks. At the end of reset, it isloaded with 0000 (divide by one), 0001 (divide by two), 0011 (divide by four), or 0111 (divide by eight)depending on the setting of the FTFA_FOPT[LPBOOT] (See Table 6-2).0000 Divide-by-1.0001 Divide-by-2.0010 Divide-by-3.0011 Divide-by-4.0100 Divide-by-5.0101 Divide-by-6.0110 Divide-by-7.0111 Divide-by-8.1000 Divide-by-9.1001 Divide-by-10.1010 Divide-by-11.1011 Divide-by-12.1100 Divide-by-13.1101 Divide-by-14.1110 Divide-by-15.1111 Divide-by-16.27–19ReservedThis field is reserved.This read-only field is reserved and always has the value 0.18–16OUTDIV4Clock 4 Output Divider valueSets the divide value for the bus and flash clock and is in addition to the System clock divide ratio. At theend of reset, it is loaded with 0001 (divide by 2).000 Divide-by-1.001 Divide-by-2.010 Divide-by-3.011 Divide-by-4.100 Divide-by-5.101 Divide-by-6.110 Divide-by-7.111 Divide-by-8.Reserved This field is reserved.This read-only field is reserved and always has the value 0.Chapter 12 System Integration Module (SIM)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 163
