Mastermode?Tx/Rx? Arbitrationlost?IAAS=1?Tx/Rx?ACK fromreceiver?SRW=1?IAAS=1?Clear ARBL2nd tolast byte to beread?Last byteto be read?RXAK=0?Last bytetransmitted?End ofaddress cycle(master Rx)?Write nextbyte to Data reg Set TXAK Generate stopsignal (MST=0)Write datato Data regSet Tx modeTransmitnext byteRead data fromData regand storeSwitch toRx modeSet Rx modeSwitch toRx modeDummy readfrom Data regGenerate stopsignal (MST=0)Read data fromData regand store Dummy readfrom Data regDummy readfrom Data regNYNNNNNNYYY YY (read)N (write)NYRxTxRxTxYNAddress transfersee note 1Data transfersee note 2NYYYNotes:1. If general call is enabled, check to determine if the received address is a general call address (0x00).If the received address is a general call address, the general call must be handled by user software.2. When 10-bit addressing addresses a slave, the slave sees an interrupt following the first byte of the extended address.Ensure that for this interrupt, the contents of the Data register are ignored and not treated as a valid data transfer.Is STOPFset?NYIs STARTFset?YNEntry of ISRClear STARTFClear IICIFLog Start Count++Clear IICIFIs this a Repeated-START(Start Count > 1)?NYRTIClear STOPFClear IICIFZero Start CountMultipleaddresses?YRead Address fromData registerand storeNFigure 36-6. Typical I2C interrupt routineInitialization/application informationKL27 Sub-Family Reference Manual , Rev. 5, 01/2016644 Freescale Semiconductor, Inc.
