ROM memory map (continued)Absoluteaddress(hex)Register name Width(in bits) Access Reset value Section/pageF000_2FD4 Peripheral ID Register (ROM_PERIPHID5) 32 R See section 43.3.3.4/882F000_2FD8 Peripheral ID Register (ROM_PERIPHID6) 32 R See section 43.3.3.4/882F000_2FDC Peripheral ID Register (ROM_PERIPHID7) 32 R See section 43.3.3.4/882F000_2FE0 Peripheral ID Register (ROM_PERIPHID0) 32 R See section 43.3.3.4/882F000_2FE4 Peripheral ID Register (ROM_PERIPHID1) 32 R See section 43.3.3.4/882F000_2FE8 Peripheral ID Register (ROM_PERIPHID2) 32 R See section 43.3.3.4/882F000_2FEC Peripheral ID Register (ROM_PERIPHID3) 32 R See section 43.3.3.4/882F000_2FF0 Component ID Register (ROM_COMPID0) 32 R See section 43.3.3.5/882F000_2FF4 Component ID Register (ROM_COMPID1) 32 R See section 43.3.3.5/882F000_2FF8 Component ID Register (ROM_COMPID2) 32 R See section 43.3.3.5/882F000_2FFC Component ID Register (ROM_COMPID3) 32 R See section 43.3.3.5/88243.3.3.1 Entry (ROM_ENTRYn)The System ROM Table begins with "n" relative 32-bit addresses, one for each debugcomponent present in the device and terminating with an all-zero value signaling the endof the table at the "n+1"-th value.It is hardwired to specific values used during the auto-discovery process by an externaldebug agent.Address: F000_2000h base + 0h offset + (4d × i), where i=0d to 2dBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R ENTRYWReset x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*ROM_ENTRYn field descriptionsField DescriptionENTRY ENTRYMemory map and register definitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016880 Freescale Semiconductor, Inc.
