pulse widthcounter overflowtimer module counter =MODperiod(2 x CnV)(2 x MOD)timer module counter = 0channel (n) match(timer module countingis down)channel (n) match(timer module countingis up)counter overflowtimer module counter =MODchannel (n) outputFigure 29-12. CPWM period and pulse width with ELSnB:ELSnA = 1:0If (ELSnB:ELSnA = 0:0) when the TPM counter reaches the value in the CnV register,the CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however thechannel (n) output is not controlled by TPM.If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the channel (n)match (TPM counter = CnV) when counting down, and it is forced low at the channel (n)match when counting up (see the following figure).TOF bit... 7 8 87 7 76 6 65 5 54 43 32 21 0 1 ...previous valueCNTchannel (n) outputcounteroverflowchannel (n) match indown counting channel (n) match inup countingchannel (n) match indown countingcounteroverflowCHnF bitMOD = 0x0008CnV = 0x0005Figure 29-13. CPWM signal with ELSnB:ELSnA = 1:0If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the channel (n)match (TPM counter = CnV) when counting down, and it is forced high at the channel (n)match when counting up (see the following figure).TOF bit... 7 8 87 7 76 6 65 5 54 43 32 21 0 1 ...previous valueCNTchannel (n) outputcounteroverflowchannel (n) match indown counting channel (n) match inup counting channel (n) match indown countingcounteroverflowCHnF bitMOD = 0x0008CnV = 0x0005Figure 29-14. CPWM signal with ELSnB:ELSnA = X:1Chapter 29 Timer/PWM Module (TPM)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 483
