x+3x+2x+1x4c.v_wxyz nextnextnextorig_1bit400v_wxyz 400v_wxyz nextnextnextrdata + 1bitrdata4c.v_wxyz rdata + 1bitCYCLE RULERhclkBME AHB Input Busmx_haddrmx_hattrmx_hwritemx_hwdatamx_hrdatamx_hreadyBME AHB Output Bussx_haddrsx_hattrsx_hwritesx_hwdatasx_hrdatasx_hreadyBME States + Datapathcontrol_state_dp1control_state_dp2reg_addr_data_dpFigure 42-7. Decorated load: load-and-set 1-bit field insert timing diagramDecorated load-and-{set, clear} 1-bit operations follow the execution template shown inthe above figure: a 2-cycle read-modify-write operation:1. Cycle x, first AHB address phase: Read from input bus is translated into a readoperation on the output bus with the actual memory address (with the decorationremoved) and then captured in a register2. Cycle x+1, second AHB address phase: Write access with the registered (but actual)memory address is output3. Cycle x+1, first AHB data phase: The "original" 1-bit memory read data is capturedin a register, while the 1-bit field is set or clear based on the function defined by thedecoration with the modified data captured in a register; the input bus cycle is stalled4. Cycle x+2, second AHB data phase: The selected original 1-bit is right-justified,zero-filled and then driven onto the input read data bus, while the registered writedata is sourced onto the output write data busFunctional descriptionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016842 Freescale Semiconductor, Inc.
