Setting FPR[FILT_PER] to 0 disables the filter and eliminates switching currentassociated with the filtering process.NoteAlways switch to this setting prior to making any changes infilter parameters. This resets the filter to a known state.Switching CR0[FILTER_CNT] on the fly without thisintermediate step can result in unexpected behavior.24.4.4.2 Latency issuesThe value of FPR[FILT_PER] or SAMPLE period must be set such that the samplingperiod is just longer than the period of the expected noise. This way a noise spike willcorrupt only one sample. The value of CR0[FILTER_CNT] must be chosen to reduce theprobability of noisy samples causing an incorrect transition to be recognized. Theprobability of an incorrect transition is defined as the probability of an incorrect sampleraised to the power of CR0[FILTER_CNT].The values of FPR[FILT_PER] or SAMPLE period and CR0[FILTER_CNT] must alsobe traded off against the desire for minimal latency in recognizing actual comparatoroutput transitions. The probability of detecting an actual output change within thenominal latency is the probability of a correct sample raised to the power ofCR0[FILTER_CNT].The following table summarizes maximum latency values for the various modes ofoperation in the absence of noise. Filtering latency is restarted each time an actual outputtransition is masked by noise.Table 24-3. Comparator sample/filter maximum latenciesMode # CR1[EN]CR1[WE]CR1[SE]CR0[FILTER_CNT]FPR[FILT_PER] Operation Maximum latency11 0 X X X X Disabled N/A2A 1 0 0 0x00 X Continuous Mode TPD2B 1 0 0 X 0x003B 1 0 0 0x01 > 0x00 Sampled, Non-Filtered mode TPD + (FPR[FILT_PER] *Tper) + Tper4B 1 0 0 > 0x01 > 0x00 Sampled, Filtered mode TPD + (CR0[FILTER_CNT] *FPR[FILT_PER] x Tper) + Tper1. TPD represents the intrinsic delay of the analog component plus the polarity select logic. Tper is the period of the bus clock.Chapter 24 Comparator (CMP)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 409
