Table 39-6. SPI Master (CPHA=0) Configuration (continued)Register Value CommentsSHIFTCTL(n+1) 0x0000_0101 Configure receive using Timer 0 onposedge of clock with input data on Pin1.TIMCMPn 0x0000_3F01 Configure 32-bit transfer with baud rateof divide by 4 of the FlexIO clock. SetTIMCMP[15:8] = (number of bits x 2) - 1.Set TIMCMP[7:0] = (baud rate divider /2) - 1.TIMCFGn 0x0100_2222 Configure start bit, stop bit, enable ontrigger high and disable on compare,initial clock state is logic 0. Set PINPOLto invert the output shift clock.TIMCTLn 0x01C3_0201 Configure dual 8-bit counter using Pin 2output (shift clock), with Shifter 0 flag asthe inverted trigger.TIMCMP(n+1) 0x0000_FFFF Never compare.TIMCFG(n+1) 0x0000_1100 Enable when Timer 0 is enabled anddisable when Timer 0 is disabled.TIMCTL(n+1) 0x0003_0383 Configure 16-bit counter (nevercompare) using inverted Pin 3 output (asslave select).SHIFTBUFn Data to transmit Transmit data can be written toSHIFTBUF, use the Shifter Status Flagto indicate when data can be writtenusing interrupt or DMA request. Cansupport MSB first transfer by writing toSHIFTBUFBBS register instead.SHIFTBUF(n+1) Data to receive Received data can be read fromSHIFTBUFBYS, use the Shifter StatusFlag to indicate when data can be readusing interrupt or DMA request. Cansupport MSB first transfer by readingfrom SHIFTBUFBIS register instead.Table 39-7. SPI Master (CPHA=1) ConfigurationRegister Value CommentsSHIFTCFGn 0x0000_0021 Start bit loads data on first shift.SHIFTCTLn 0x0003_0002 Configure transmit using Timer 0 onposedge of clock with output data on Pin0.SHIFTCFG(n+1) 0x0000_0000 Start and stop bit disabled.SHIFTCTL(n+1) 0x0080_0101 Configure receive using Timer 0 onnegedge of clock with input data on Pin1.TIMCMPn 0x0000_3F01 Configure 32-bit transfer with baud rateof divide by 4 of the FlexIO clock. SetTIMCMP[15:8] = (number of bits x 2) - 1.Table continues on the next page...Application InformationKL27 Sub-Family Reference Manual , Rev. 5, 01/2016776 Freescale Semiconductor, Inc.
