SAMPLESRx pin inputRT CLOCKRT CLOCK COUNTRESET RT CLOCK1 1 1 0 1 0 0 0START BIT LSBRT1RT1RT1RT1RT2RT4RT3RT5RT1RT1RT2RT3RT10RT1RT2RT31 1 0 0 0 0RT11RT12RT13RT14RT15RT16RT4RT5RT6RT7RT8RT9Figure 38-4. Start bit search example 1 (C7816[ISO_7816E] = 0)In the following figure, verification sample at RT3 is high. In this exampleC7816[ISO_7816E] = 0. The RT3 sample sets the noise flag. Although the perceived bittime is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and datarecovery is successful.SAMPLESRx pin inputRT CLOCKRT CLOCK COUNTRESET RT CLOCK1 1 1 0 1 0 0 0PERCEIVED START BITACTUAL START BIT LSBRT1RT1RT1RT1RT1RT2RT1RT3RT4RT5RT6RT7RT13RT12RT11RT14RT1RT2RT3RT4RT5RT6RT71 1 0 0RT10RT8RT9RT15RT16Figure 38-5. Start bit search example 2 (C7816[ISO_7816E] = 0)In the following figure, a large burst of noise is perceived as the beginning of a start bit,although the test sample at RT5 is high. In this example C7816[ISO_7816E] = 0. TheRT5 sample sets the noise flag. Although this is a worst-case misalignment of perceivedbit time, the data samples RT8, RT9, and RT10 are within the bit time and data recoveryis successful.Chapter 38 Universal Asynchronous Receiver/Transmitter(UART)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 717
