CADIN = Internal ADC input capacitanceNUMTAU = -ln(LSBERR / 2N)LSBERR = value of acceptable sampling error in LSBsN = 8 in 8-bit mode, 10 in 10-bit mode, 12 in 12-bit mode or 16 in 16-bit modeHigher source resistances or higher-accuracy sampling is possible by settingCFG1[ADLSMP] and changing CFG2[ADLSTS] to increase the sample window, ordecreasing ADCK frequency to increase sample time.23.7.2.2 Pin leakage errorLeakage on the I/O pins can cause conversion error if the external analog sourceresistance, RAS, is high. If this error cannot be tolerated by the application, keep RASlower than VREFH / (4 × ILEAK × 2N) for less than 1/4 LSB leakage error, where N = 8 in8-bit mode, 10 in 10-bit mode, 12 in 12-bit mode, or 16 in 16-bit mode.23.7.2.3 Noise-induced errorsSystem noise that occurs during the sample or conversion process can affect the accuracyof the conversion. The ADC accuracy numbers are guaranteed as specified only if thefollowing conditions are met:• There is a 0.1 μF low-ESR capacitor from VREFH to VREFL.• There is a 0.1 μF low-ESR capacitor from VDDA to VSSA.• If inductive isolation is used from the primary supply, an additional 1 μF capacitor isplaced from VDDA to VSSA.• VSSA, and VREFL, if connected, is connected to VSS at a quiet point in the groundplane.• Operate the MCU in Wait or Normal Stop mode before initiating (hardware-triggeredconversions) or immediately after initiating (hardware- or software-triggeredconversions) the ADC conversion.Application informationKL27 Sub-Family Reference Manual , Rev. 5, 01/2016386 Freescale Semiconductor, Inc.
