I2Sx_RCSR field descriptions (continued)Field DescriptionEnables/disables the receiver. When software clears this field, the receiver remains enabled, and this bitremains set, until the end of the current frame.0 Receiver is disabled.1 Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.30STOPEStop EnableConfigures receiver operation in Stop mode. This bit is ignored and the receiver is disabled in all low-leakage stop modes.0 Receiver disabled in Stop mode.1 Receiver enabled in Stop mode.29DBGEDebug EnableEnables/disables receiver operation in Debug mode. The receive bit clock is not affected by Debug mode.0 Receiver is disabled in Debug mode, after completing the current frame.1 Receiver is enabled in Debug mode.28BCEBit Clock EnableEnables the receive bit clock, separately from RE. This field is automatically set whenever RE is set.When software clears this field, the receive bit clock remains enabled, and this field remains set, until theend of the current frame.0 Receive bit clock is disabled.1 Receive bit clock is enabled.27–26ReservedThis field is reserved.This read-only field is reserved and always has the value 0.25FRFIFO ResetResets the FIFO pointers. Reading this field will always return zero. FIFO pointers should only be resetwhen the receiver is disabled or the FIFO error flag is set.0 No effect.1 FIFO reset.24SRSoftware ResetResets the internal receiver logic including the FIFO pointers. Software-visible registers are not affected,except for the status registers.0 No effect.1 Software reset.23–21ReservedThis field is reserved.This read-only field is reserved and always has the value 0.20WSFWord Start FlagIndicates that the start of the configured word has been detected. Write a logic 1 to this field to clear thisflag.0 Start of word not detected.1 Start of word detected.Table continues on the next page...Memory map and register definitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016802 Freescale Semiconductor, Inc.
