NOTEThe format of this mask field is different thanMTBDWT_MASKn[MASK].Address: F000_0000h base + 4h offset = F000_0004hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16REN0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0HALTREQRAMPRIVSFRWPRIVTSTOPENTSTARTENMASKWReset 0 0 0 0 0 0 0 0 1 0 0 x* x* x* x* x** Notes:x = Undefined at reset.•MTB_MASTER field descriptionsField Description31ENMain Trace EnableWhen this field is 1, trace data is written into the RAM memory location addressed byMTB_POSITION[POINTER]. The MTB_POSITION[POINTER] value auto increments after the trace datapacket is written.EN can be automatically set to 0 using the MTB_FLOW[WATERMARK] field and theMTB_FLOW[AUTOSTOP] bit.EN is automatically set to 1 if TSTARTEN is 1 and the TSTART signal is HIGH.EN is automatically set to 0 if TSTOPEN is 1 and the TSTOP signal is HIGH.NOTE: If EN is set to 0 because MTB_FLOW[WATERMARK] is set, then it is not automatically set to 1 ifTSTARTEN is 1 and the TSTART input is HIGH. In this case, tracing can only be restarted ifMTB_FLOW[WATERMARK] or MTB_POSITION[POINTER] value is changed by software.30–10ReservedThis field is reserved.This read-only field is reserved and always has the value 0.9HALTREQHalt RequestThis field is connected to the halt request signal of the trace logic, EDBGRQ. When HALTREQ is set to 1,the EDBFGRQ is asserted if DBGEN (invasive debug enable, one of the debug authentication interfacesignals) is also HIGH. HALTREQ can be automatically set to 1 using MTB_FLOW[WATERMARK].8RAMPRIVRAM PrivilegeIf this field is 0, then user or privileged AHB read and write accesses to the RAM are permitted. If this fieldis 1, then only privileged AHB read and write accesses to the RAM are permitted and user accesses areRAZ/WI. The HPROT[1] signal determines if an access is a user or privileged mode reference.Table continues on the next page...Memory map and register definitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016860 Freescale Semiconductor, Inc.
