38.5.2.3 Character receptionDuring UART reception, the receive shift register shifts a frame in from theunsynchronized receiver input signal. After a complete frame shifts into the receive shiftregister, the data portion of the frame transfers to the UART receive buffer. The receivedata buffer is accessible via the D and C3[T8] registers. S1[RDRF] is set if the receivebuffer is full. If the C2[RIE] is also set, RDRF generates an RDRF interrupt request.Alternatively, by programming C5[RDMAS], a DMA request can be generated.When C7816[ISO_7816E] is set/enabled and C7816[TTYPE] = 0, character receptionoperates slightly differently. Upon receipt of the parity bit, the validity of the parity bit ischecked. If C7816[ANACK] is set and the parity check fails, or if INIT and the receivedcharacter is not a valid initial character, then a NACK is sent by the receiver. If thenumber of consecutive receive errors exceeds the threshold set byET7816[RXTHRESHOLD], then IS7816[RXT] is set and an interrupt generated ifIE7816[RXTE] is set. If an error is detected due to parity or an invalid initial character,the data is not transferred from the receive shift register to the receive buffer. Instead, thedata is overwritten by the next incoming data.When the C7816[ISO_7816E] is set/enabled, C7816[ONACK] is set/enabled, and thereceived character results in the receive buffer overflowing, a NACK is issued by thereceiver. Additionally, S1[OR] is set and an interrupt is issued if required, and the data inthe shift register is discarded.38.5.2.4 Data samplingThe receiver samples the unsynchronized receiver input signal at the RT clock rate. TheRT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baudrate mismatch, the RT clock (see the following figure) is re-synchronized:• After every start bit.• After the receiver detects a data bit change from logic 1 to logic 0 (after the majorityof data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority ofthe next RT8, RT9, and RT10 samples returns a valid logic 0).To locate the start bit, data recovery logic does an asynchronous search for a logic 0preceded by three logic 1s. When the falling edge of a possible start bit occurs, the RTclock begins to count to 16.Functional descriptionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016714 Freescale Semiconductor, Inc.
