14.5.3.1 RUN modeThis is the normal operating mode for the device.This mode is selected after any reset. When the ARM processor exits reset, it sets up thestack, program counter (PC), and link register (LR):• The processor reads the start SP (SP_main) from vector-table offset 0x000• The processor reads the start PC from vector-table offset 0x004• LR is set to 0xFFFF_FFFF.To reduce power in this mode, disable the clocks to unused modules using theircorresponding clock gating control bits in the SIM's (or PCC's) registers.14.5.3.2 Very-Low Power Run (VLPR) modeIn VLPR mode, the on-chip voltage regulator is put into a stop mode regulation state. Inthis state, the regulator is designed to supply enough current to the MCU over a reducedfrequency. To further reduce power in this mode, disable the clocks to unused modulesusing their corresponding clock gating control bits in the SIM's registers.Before entering this mode, the following conditions must be met:• The MCG must be configured in a mode which is supported during VLPR. See thePower Management details for information about these MCG modes.• All clock monitors in the MCG must be disabled.• The maximum frequencies of the system, bus, flash, and core are restricted. See thePower Management details about which frequencies are supported.• Mode protection must be set to allow VLP modes, that is, PMPROT[AVLP] is 1.• PMCTRL[RUNM] must be set to 10b to enter VLPR.• Flash programming/erasing is not allowed.NOTEDo not increase the clock frequency while in VLPR mode,because the regulator is slow in responding and cannot managefast load transitions. In addition, do not modify the clock sourcein the MCG module or any clock divider registers. Moduleclock enables in the SIM can be set, but not cleared.Chapter 14 System Mode Controller (SMC)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 235
