The Timer Configuration Register (TIMCFGn) should be configured before setting theTimer Mode (TIMOD). Once the TIMOD is configured for the desired mode, when thecondition configured by timer enable (TIMENA) is detected then the following eventsoccur.• Timer counter will load the current value of the Compare Register and startdecrementing as configured by TIMDEC.• Timer output will set depending on the TIMOUT configuration.• Transmit shifters controlled by this timer will either output their start bit value, orload the shift register from the shift buffer and output the first bit, as configured bySSTART.The Timer will then generate the timer output and timer shift clock depending on theTIMOD and TIMDEC fields. The shifter clock is either equal to the timer output (whenTIMDEC=00 or 01) or equal to the decrement clock (when TIMDEC=10 or 11). WhenTIMDEC is configured to decrement from a pin or trigger, the timer will decrement onboth rising and falling edges.When the Timer is configured to reset as configured in the TIMRST field then the Timercounter will load the current value of the Compare Register again, the timer output mayalso be affected by the reset as configured in TIMOUT.If the Timer start bit is enabled, the timer counter will reload with the compare register onthe first rising edge of the shift clock after the timer starts decrementing. If there is nofalling edge on the shift clock before the first rising edge (for example, whenTIMOUT=1), a shifter that is configured to shift on falling edge and load on the first shiftwill not load correctly.When configured for 8-bit counter mode, whenever the lower 8-bit counter decrements tozero the timer output will toggle, the lower 8-bit counter register will reload from thecompare register and the upper 8-bit counter will decrement. For 8-bit PWM mode, thelower 8-bit counter will only decrement when the output is high and the upper 8-bitcounter will only decrement when the output is low. The timer output will togglewhenever either lower or upper 8-bit counter decrements to zero.When the timer decrements to zero, a compare event occurs depending on the timermode. For 8-bit counter or PWM modes, both halves of the counter must equal zero andthe upper half must decrement for the timer compare event to occur, while in 16-bit modethe entire counter must equal zero and decrement. The timer compare event will cause thetimer status flag to set, the timer counter to load the contents of the timer compareregister, the timer output to toggle, any configured transmit shift registers to load and anyconfigured receive shift registers to store .When the is Timer is configured to add a stop bit on each compare, the followingadditional events will occur.Functional descriptionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016770 Freescale Semiconductor, Inc.
