SPIx_C2 field descriptions (continued)Field Description0 DMA request for transmit is disabled and interrupt from SPTEF is allowed1 DMA request for transmit is enabled and interrupt from SPTEF is disabled4MODFENMaster Mode-Fault Function EnableWhen the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slaveselect input.) In master mode, this bit determines how the SS pin is used. For details, refer to thedescription of the SSOE bit in the C1 register.0 Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI1 Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output3BIDIROEBidirectional Mode Output EnableWhen bidirectional mode is enabled because SPI pin control 0 (SPC0) is set to 1, BIDIROE determineswhether the SPI data output driver is enabled to the single bidirectional SPI I/O pin. Depending on whetherthe SPI is configured as a master or a slave, it uses the MOSI (MOMI) or MISO (SISO) pin, respectively,as the single SPI data I/O pin. When SPC0 is 0, BIDIROE has no meaning or effect.0 Output driver disabled so SPI data I/O pin acts as an input1 SPI I/O pin enabled as an output2RXDMAEReceive DMA enableThis is the enable bit for a receive DMA request. When this bit is set to 1, a receive DMA request isasserted when both SPRF and SPE are set, and the interrupt from SPRF is disabled.0 DMA request for receive is disabled and interrupt from SPRF is allowed1 DMA request for receive is enabled and interrupt from SPRF is disabled1SPISWAISPI Stop in Wait ModeThis bit is used for power conservation while the device is in Wait mode.0 SPI clocks continue to operate in Wait mode.1 SPI clocks stop when the MCU enters Wait mode.0SPC0SPI Pin Control 0Enables bidirectional pin configurations.0 SPI uses separate pins for data input and data output (pin mode is normal).In master mode of operation: MISO is master in and MOSI is master out.In slave mode of operation: MISO is slave out and MOSI is slave in.1 SPI configured for single-wire bidirectional operation (pin mode is bidirectional).In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 ormaster I/O when BIDIROE is 1.In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1;MOSI is not used by SPI.Memory map/register definitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016580 Freescale Semiconductor, Inc.
