For core configurations like that supported by Cortex-M0+, ARM recommends that adebugger identifies and connects to the debug components using the CoreSight debuginfrastructure.ARM recommends that a debugger follows the flow as shown in the following figure todiscover the components in the CoreSight debug infrastructure. In this case, a debuggerreads the peripheral and component ID registers for each CoreSight component in theCoreSight system.CoreSight access portBase pointerRedirection from theSystem ROM table, if implemented++Flycatcher ROM tableCoreSight IDPointersSystem control spaceCoreSight IDFlycatcher CPUIDDebug controlData watchpoint unitCoreSight IDWatchpoint control++ Breakpoint unitCoreSight IDBreakpoint control++Optional component++Figure 43-3. CoreSight discovery processROM memory mapAbsoluteaddress(hex)Register name Width(in bits) Access Reset value Section/pageF000_2000 Entry (ROM_ENTRY0) 32 R See section 43.3.3.1/880F000_2004 Entry (ROM_ENTRY1) 32 R See section 43.3.3.1/880F000_2008 Entry (ROM_ENTRY2) 32 R See section 43.3.3.1/880F000_200C End of Table Marker Register (ROM_TABLEMARK) 32 R 0000_0000h 43.3.3.2/881F000_2FCC System Access Register (ROM_SYSACCESS) 32 R 0000_0001h 43.3.3.3/881F000_2FD0 Peripheral ID Register (ROM_PERIPHID4) 32 R See section 43.3.3.4/882Table continues on the next page...Chapter 43 Micro Trace Buffer (MTB)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 879
