The WFI or WFE instruction is used to invoke Sleep and Deep Sleep modes. Run, Wait,and Stop are the common terms used for the primary operating modes of Freescalemicrocontrollers.The following table shows the translation between the ARM CPU modes and theFreescale MCU power modes.ARM CPU mode MCU modeSleep WaitDeep Sleep StopAccordingly, the ARM CPU documentation refers to sleep and deep sleep, while theFreescale MCU documentation normally uses wait and stop.In addition, Freescale MCUs also augment Stop, Wait, and Run modes in a number ofways. The power management controller (PMC) contains a run and a stop moderegulator. Run regulation is used in normal run, wait and stop modes. Stop moderegulation is used during all very low power and low leakage modes. During stop moderegulation, the bus frequencies are limited in the very low power modes.The SMC provides the user with multiple power options. The Very Low Power Run(VLPR) mode can drastically reduce run time power when maximum bus frequency isnot required to handle the application needs. From Normal Run mode, the Run Mode(RUNM) field can be modified to change the MCU into VLPR mode when limitedfrequency is sufficient for the application. From VLPR mode, a corresponding wait(VLPW) and stop (VLPS) mode can be entered.Depending on the needs of the user application, a variety of stop modes are available thatallow the state retention, partial power down or full power down of certain logic and/ormemory. I/O states are held in all modes of operation. Several registers are used toconfigure the various modes of operation for the device.The following table describes the power modes available for the device.Table 14-1. Power modesMode DescriptionRUN The MCU can be run at full speed and the internal supply is fully regulated, that is, in run regulation.This mode is also referred to as Normal Run mode.WAIT The core clock is gated off. The system clock continues to operate. Bus clocks, if enabled, continueto operate. Run regulation is maintained.STOP The core clock is gated off. System clocks to other masters and bus clocks are gated off after allstop acknowledge signals from supporting peripherals are valid.VLPR The core, system, bus, and flash clock maximum frequencies are restricted in this mode. See thePower Management chapter for details about the maximum allowable frequencies.Table continues on the next page...Modes of operationKL27 Sub-Family Reference Manual , Rev. 5, 01/2016224 Freescale Semiconductor, Inc.
