Table 14-2. Power mode transition triggers (continued)Transition # From To Trigger conditionsSleep-now or sleep-on-exit modes entered with SLEEPDEEPset, which is controlled in System Control Register in ARMcore.See note.1STOP RUN Interrupt or Reset3 RUN VLPR The core, system, bus and flash clock frequencies and MCGclocking mode are restricted in this mode. See the PowerManagement chapter for the maximum allowable frequenciesand MCG modes supported.Set PMPROT[AVLP]=1, PMCTRL[RUNM]=10.VLPR RUN Set PMCTRL[RUNM]=00 orReset.4 VLPR VLPW Sleep-now or sleep-on-exit modes entered with SLEEPDEEPclear, which is controlled in System Control Register in ARMcore.See note.1VLPW VLPR Interrupt5 VLPW RUN Reset6 VLPR VLPS PMCTRL[STOPM]=0003 or 010,Sleep-now or sleep-on-exit modes entered with SLEEPDEEPset, which is controlled in System Control Register in ARMcore.See note.1VLPS VLPR InterruptNOTE: If VLPS was entered directly from RUN (transition#7), hardware forces exit back to RUN and does notallow a transition to VLPR.7 RUN VLPS PMPROT[AVLP]=1, PMCTRL[STOPM]=010,Sleep-now or sleep-on-exit modes entered with SLEEPDEEPset, which is controlled in System Control Register in ARMcore.See note.1VLPS RUN Interrupt and VLPS mode was entered directly from RUN orReset8 RUN VLLSx PMPROT[AVLLS]=1, PMCTRL[STOPM]=100,STOPCTRL[LLSM]=x (VLLSx), Sleep-now or sleep-on-exitmodes entered with SLEEPDEEP set, which is controlled inSystem Control Register in ARM core.VLLSx RUN Wakeup from enabled LLWU input source or RESET pin9 VLPR VLLSx PMPROT[AVLLS]=1, PMCTRL[STOPM]=100,STOPCTRL[LLSM]=x (VLLSx), Sleep-now or sleep-on-exitmodes entered with SLEEPDEEP set, which is controlled inSystem Control Register in ARM core.Table continues on the next page...Functional descriptionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016232 Freescale Semiconductor, Inc.
