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DMA_DCRn field descriptions (continued)Field Descriptionboundary depends on the initial destination address (DAR). The base address should be aligned to a 0-modulo-(circular buffer size) boundary. Misaligned buffers are not possible. The boundary is forced to thevalue determined by the upper address bits in the field selection.0000 Buffer disabled0001 Circular buffer size is 16 bytes0010 Circular buffer size is 32 bytes0011 Circular buffer size is 64 bytes0100 Circular buffer size is 128 bytes0101 Circular buffer size is 256 bytes0110 Circular buffer size is 512 bytes0111 Circular buffer size is 1 KB1000 Circular buffer size is 2 KB1001 Circular buffer size is 4 KB1010 Circular buffer size is 8 KB1011 Circular buffer size is 16 KB1100 Circular buffer size is 32 KB1101 Circular buffer size is 64 KB1110 Circular buffer size is 128 KB1111 Circular buffer size is 256 KB7D_REQDisable RequestDMA hardware automatically clears the corresponding DCRn[ERQ] bit when the byte count registerreaches 0.0 ERQ bit is not affected.1 ERQ bit is cleared when the BCR is exhausted.6ReservedThis field is reserved.This read-only field is reserved and always has the value 0.5–4LINKCCLink Channel ControlAllows DMA channels to have their transfers linked. The current DMA channel triggers a DMA request tothe linked channels (LCH1 or LCH2) depending on the condition described by the LINKCC bits.If not in cycle steal mode (DCRn[CS]=0) and LINKCC equals 01 or 10, no link to LCH1 occurs.If LINKCC equals 01, a link to LCH1 is created after each cycle-steal transfer performed by the currentDMA channel is completed. As the last cycle-steal is performed and the BCR reaches zero, then the link toLCH1 is closed and a link to LCH2 is created.00 No channel-to-channel linking01 Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after theBCR decrements to 0.10 Perform a link to channel LCH1 after each cycle-steal transfer11 Perform a link to channel LCH1 after the BCR decrements to 0.3–2LCH1Link Channel 1Indicates the DMA channel assigned as link channel 1. The link channel number cannot be the same asthe currently executing channel, and generates a configuration error if this is attempted (DSRn[CE] is set).00 DMA Channel 001 DMA Channel 1Table continues on the next page...Memory Map/Register DefinitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016318 Freescale Semiconductor, Inc.