After SPRF is set, it does not clear until it is serviced. SPRF has an automatic clearingprocess that is described in the SPI Status Register details. If the SPRF is not servicedbefore the end of the next transfer (that is, SPRF remains active throughout anothertransfer), the subsequent transfers are ignored and no new data is copied into the Dataregister.35.5.13.3 SPTEFSPTEF occurs when the SPI transmit buffer is ready to accept new data. In 8-bit mode,SPTEF is set only after all 8 bits have been moved from SPIx_DL into the shifter. In 16-bit mode, SPTEF is set only after all 16 bits have been moved from SPIx_DH:SPIx_DLinto the shifter.After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearingprocess that is described in the SPI Status Register details.35.5.13.4 SPMFSPMF occurs when the data in the receive data buffer is equal to the data in the SPIMatch Register. In 8-bit mode, SPMF is set only after bits 7–0 in the receive data bufferare determined to be equivalent to the value in SPIx_ML. In 16-bit mode, SPMF is setafter bits 15–0 in the receive data buffer are determined to be equivalent to the value inSPIx_MH:SPIx_ML.35.5.13.5 TNEAREFThe TNEAREF bit applies when the FIFO feature is supported.The TNEAREF flag is set when only one 16-bit word or two 8-bit bytes of data remain inthe transmit FIFO provided C3[5] = 0 or when only two 16-bit words or four 8-bit bytesof data remain in the transmit FIFO provided C3[5] =1. If FIFOMODE is not enabled,ignore this bit.Clearing this interrupt depends on the state of C3[3] and the status of TNEAREF. Referto the description of the SPI status (S) register.35.5.13.6 RNFULLFThe RNFULLF bit applies when the FIFO feature is supported.Functional descriptionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016604 Freescale Semiconductor, Inc.
