in (on the MISO pin) from the slave. The transfer effectively exchanges the data that wasin the SPI shift registers of the two SPI systems. The SPSCK signal is a clock outputfrom the master and an input to the slave. The slave device must be selected by a lowlevel on the slave select input (SS pin). In this system, the master device has configuredits SS pin as an optional slave select output.SPI SHIFTERMASTER8 OR 16 BITSCLOCKGENERATORMOSIMISO MISOMOSISPSCK SPSCKSS SSSLAVESPI SHIFTER8 OR 16 BITSFigure 35-1. SPI system connections35.2.3.2 SPI module block diagramThe following is a block diagram of the SPI module. The central element of the SPI is theSPI shift register. Data is written to the double-buffered transmitter (write toSPIx_DH:SPIx_DL) and gets transferred to the SPI Shift Register at the start of a datatransfer. After shifting in 8 bits or 16 bits (as determined by the SPIMODE bit) of data,the data is transferred into the double-buffered receiver where it can be read fromSPIx_DH:SPIx_DL. Pin multiplexing logic controls connections between MCU pins andthe SPI module.When the FIFO feature is supported: Additionally there is an 8-byte receive FIFO and an8-byte transmit FIFO that (once enabled) provide features to allow fewer CPU interruptsto occur when transmitting/receiving high volume/high speed data. When FIFO mode isenabled, the SPI can still function in either 8-bit or 16-bit mode (as per SPIMODE bit)and three additional flags help monitor the FIFO status. Two of these flags can provideCPU interrupts.When the SPI is configured as a master, the clock output is routed to the SPSCK pin, theshifter output is routed to MOSI, and the shifter input is routed from the MISO pin.IntroductionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016570 Freescale Semiconductor, Inc.
