DMA_DCRn field descriptions (continued)Field DescriptionDetermines whether an interrupt is generated by completing a transfer or by the occurrence of an errorcondition.0 No interrupt is generated.1 Interrupt signal is enabled.30ERQEnable Peripheral RequestCAUTION: Be careful: a collision can occur between START and D_REQ when ERQ is 1.0 Peripheral request is ignored.1 Enables peripheral request to initiate transfer. A software-initiated request (setting START) is alwaysenabled.29CSCycle Steal0 DMA continuously makes read/write transfers until the BCR decrements to 0.1 Forces a single read/write transfer per request.28AAAuto-alignAA and SIZE bits determine whether the source or destination is auto-aligned; that is, transfers areoptimized based on the address and size.0 Auto-align disabled1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise,destination accesses are auto-aligned. Source alignment takes precedence over destinationalignment. If auto-alignment is enabled, the appropriate address register increments, regardless ofDINC or SINC.27–25ReservedThis field is reserved.This read-only field is reserved and always has the value 0.24ReservedThis field is reserved.CAUTION: Must be written as zero; otherwise, undefined behavior results.23EADREQEnable asynchronous DMA requestsEnables the channel to support asynchronous DREQs while the MCU is in Stop mode.0 Disabled1 Enabled22SINCSource IncrementControls whether the source address increments after each successful transfer.0 No change to SAR after a successful transfer.1 The SAR increments by 1, 2, 4 as determined by the transfer size.21–20SSIZESource SizeDetermines the data size of the source bus cycle for the DMA controller.00 32-bit01 8-bitTable continues on the next page...Memory Map/Register DefinitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016316 Freescale Semiconductor, Inc.
