1. PORT clock gate, pin mux and peripheral registers are not reset to default values onROM exitDescription• Affected PORT clock gates: PORTA, PORTB, PORTC, PORTD and PORTE(SIM_SCGC5_PORTA, SIM_SCGC5_PORTB, SIM_SCGC5_PORTC,SIM_SCGC5_PORTD and SIM_SCGC5_PORTE are enabled)• Affected pin mux: LPUART0(PTA1, PTA2), I2C0(PTB0,PTB1),SPI0(PTC4,PTC5,PTC6,PTC7)• Affected peripheral registers:• UART and UART clock source (SIM_SOPT2_UART0SRC = 3)• SPI• I2CWorkaround• User must re-configure corresponding register to expected value instead ofrelying on the default value.2. UART cannot work at 57600 baudrate with default core clockWorkaround• Send ping packet bytes continuously without delay• Limit highest UART clock frequency to 38400 at default clock (8 MHz)• To improve UART throughput, configure the core clock to higher frequency3. COP is disabled in ROM and it cannot be re-enabled by an application that isjumped-to from ROMDescription• SIM_COPC register is write once when out of reset, it is disabled in ROM• User application cannot re-enable it if application is run by jumping from ROMWorkaround• Set FOPT[BOOTSRC_SEL] = 00b, FOPT[BOOTPIN_OPT]= 0b• With above settings, boot source of chip is selected by assertion of NMI pin; ifNMI pin is not asserted during POR reset / Chip reset, chip will boot from flashand COP can be enabled.Bootloader errataKL27 Sub-Family Reference Manual , Rev. 5, 01/2016222 Freescale Semiconductor, Inc.
