The receive shift register will assert an error interrupt if a NACK is detected, but softwareis responsible for generating the STOP or repeated START condition. If a NACK isdetected during master-transmit, the interrupt routine should immediately write thetransmit shifter register with 0x00 (if generating STOP) or 0xFF (if generating repeatedSTART). Software should then wait for the next rising edge on SCL and then disableboth timers. The transmit shifter should then be disabled after waiting the setup delay fora repeated START or STOP condition.Due to synchronization delays, the data valid time for the transmit output is 2 FlexIOclock cycles, so the maximum baud rate is divide by 6 of the FlexIO clock frequency.The I2C master data valid is delayed 2 cycles because the clock output is passed througha synchronizer before clocking the transmit/receive shifter (to guarantee some SDA holdtime). Since the SCL output is synchronous with FlexIO clock, the synchronization delayis 1 cycle and then 1 cycle to generate the output.Table 39-10. I2C Master ConfigurationRegister Value CommentsSHIFTCFGn 0x0000_0032 Start bit enabled (logic 0) and stop bitenabled (logic 1).SHIFTCTLn 0x0101_0082 Configure transmit using Timer 1 onrising edge of clock with inverted outputenable (open drain output) on Pin 0.SHIFTCFG(n+1) 0x0000_0020 Start bit disabled and stop bit enabled(logic 0) for ACK/NACK detection.SHIFTCTL(n+1) 0x0180_0001 Configure receive using Timer 1 onfalling edge of clock with input data onPin 0.TIMCMPn 0x0000_2501 Configure 2 word transfer with baud rateof divide by 4 of the FlexIO clock. SetTIMCMP[15:8] = (number of words x 18)+ 1. Set TIMCMP[7:0] = (baud ratedivider / 2) - 1.TIMCFGn 0x0102_2222 Configure start bit, stop bit, enable ontrigger high, disable on compare, reset ifoutput equals pin. Initial clock state islogic 0 and is not affected by reset.TIMCTLn 0x01C1_0101 Configure dual 8-bit counter using Pin 1output enable (SCL open drain), withShifter 0 flag as the inverted trigger.TIMCMP(n+1) 0x0000_000F Configure 8-bit transfer. SetTIMCMP[15:0] = (number of bits x 2) - 1.TIMCFG(n+1) 0x0020_1112 Enable when Timer 0 is enabled, disablewhen Timer 0 is disabled, enable startbit and stop bit at end of each word,decrement on pin input.TIMCTL(n+1) 0x01C0_0183 Configure 16-bit counter using invertedPin 1 input (SCL).Table continues on the next page...Application InformationKL27 Sub-Family Reference Manual , Rev. 5, 01/2016780 Freescale Semiconductor, Inc.
