The resulting conversion time is generated using the parameters listed in the precedingtable. Therefore, for bus clock equal to 8 MHz and ADCK equal to 1 MHz, the resultingconversion time is 57.625 μs, that is, AverageNum. This results in a total conversion timeof 1.844 ms.23.5.4.6.3 Short conversion time configurationA configuration for short ADC conversion is:• 8-bit Single-Ended mode with the bus clock selected as the input clock source• The input clock divide-by-1 ratio selected• Bus frequency of 20 MHz• Long sample time disabled• High-speed conversion enabledThe conversion time for this conversion is calculated by using the Equation 1 on page370, and the information provided in Table 23-5 through Table 23-9. The table belowlists the variables of Equation 1 on page 370.Table 23-12. Typical conversion timeVariable TimeSFCAdder 5 ADCK cycles + 5 bus clock cyclesAverageNum 1BCT 17 ADCK cyclesLSTAdder 0 ADCK cyclesHSCAdder 2The resulting conversion time is generated using the parameters listed in in the precedingtable. Therefore, for bus clock and ADCK frequency equal to 20 MHz, the resultingconversion time is 1.45 μs.23.5.4.7 Hardware average functionThe hardware average function can be enabled by setting SC3[AVGE]=1 to perform ahardware average of multiple conversions. The number of conversions is determined bythe AVGS[1:0] bits, which can select 4, 8, 16, or 32 conversions to be averaged. Whilethe hardware average function is in progress, SC2[ADACT] will be set.After the selected input is sampled and converted, the result is placed in an accumulatorfrom which an average is calculated once the selected number of conversions have beencompleted. When hardware averaging is selected, the completion of a single conversionwill not set SC1n[COCO].Chapter 23 Analog-to-Digital Converter (ADC)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 373
