35.5.5.1 Transmit by DMATransmit by DMA is supported only when TXDMAE is set. A transmit DMA request isasserted when both SPE and SPTEF are set. Then the on-chip DMA controller detectsthis request and transfers data from memory into the SPI data register. After that, TXDMA DONE is asserted to clear SPTEF automatically. This process repeats until all datafor transmission (the number is decided by the configuration register[s] of the DMAcontroller) is sent.When the FIFO feature is supported: In FIFO mode (FIFOMODE=1) and when a datalength of 8 bits is selected (SPIMODE=0), the DMA transfer for one transmit DMArequest can write more than 1 byte (up to 8 bytes) to the DL register because the TXFIFO can store 8 bytes of transmit data. In FIFO mode (FIFOMODE=1) and when a datalength of 16 bits is selected (SPIMODE=1), the DMA transfer for one transmit DMArequest can write more than 1 word (up to 4 words) to the DH:DL registers because theTX FIFO can store 4 words of transmit data. A larger number of bytes or wordstransferred from memory to the SPI data register for each transmit DMA request resultsin a lower total number of transmit DMA requests.When FIFOMODE is 0: Cycle Steal (DMA_DCRn[CS] = 1) should be enabled whenusing the DMA controller to transfer data from memory to the SPI data register. TheDMA performs a single data transfer per DMA request in cycle steal mode. Therefore, asingle byte/word is written to the SPI data register from memory and transmitted by theSPI module for each DMA request, as long as the BCR value is greater than zero(DMA_DSR_BCRn[BCR] > 0). Once the BCR has reached zero, software mustreconfigure the DMA controller if more data is to be transmitted. If a configuration erroroccurs (DMA_DSR_BCRn[CE] = 1) when the BCR is equal to 0, software must:• disable peripheral requests when the BCR is equal to 0,• perform 16-bit transfers (SPIMODE = 1), or• decrease the SPI baud rate.Software can disable peripheral requests by setting DMA_DCRn[D_REQ] = 1 wheninitializing the DMA controller, or by clearing DMA_DCRn[ERQ] once the BCR isequal to zero. Also, to continue transmitting data software must re-enable peripheralrequests (DMA_DCRn[ERQ] = 1) after reconfiguring the DMA controller.35.5.5.2 Receive by DMAReceive by DMA is supported only when RXDMAE is set. A receive DMA request isasserted when both SPE and SPRF are set. Then the on-chip DMA controller detects thisrequest and transfers data from the SPI data register into memory. After that, RX DMADONE is asserted to clear SPRF automatically. This process repeats until all data to beChapter 35 Serial Peripheral Interface (SPI)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 593
