I2Sx_TCR4 field descriptions (continued)Field Description28FCONTFIFO Continue on ErrorConfigures when the SAI will continue transmitting after a FIFO error has been detected.0 On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has beencleared.1 On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after theFIFO warning flag has been cleared.27–26ReservedThis field is reserved.This read-only field is reserved and always has the value 0.25–24FPACKFIFO Packing ModeEnables packing of 8-bit data or 16-bit data into each 32-bit FIFO word. If the word size is greater than 8-bit or 16-bit then only the first 8-bit or 16-bits are loaded from the FIFO. The first word in each framealways starts with a new 32-bit FIFO word and the first bit shifted must be configured within the firstpacked word. When FIFO packing is enabled, the FIFO write pointer will only increment when the full 32-bit FIFO word has been written by software.00 FIFO packing is disabled01 Reserved10 8-bit FIFO packing is enabled11 16-bit FIFO packing is enabled23–17ReservedThis field is reserved.This read-only field is reserved and always has the value 0.16FRSZFrame sizeConfigures the number of words in each frame. The value written must be one less than the number ofwords in the frame. For example, write 0 for one word per frame. The maximum supported frame size is 2words.15–13ReservedThis field is reserved.This read-only field is reserved and always has the value 0.12–8SYWDSync WidthConfigures the length of the frame sync in number of bit clocks. The value written must be one less thanthe number of bit clocks. For example, write 0 for the frame sync to assert for one bit clock only. The syncwidth cannot be configured longer than the first word of the frame.7–5ReservedThis field is reserved.This read-only field is reserved and always has the value 0.4MFMSB FirstConfigures whether the LSB or the MSB is transmitted first.0 LSB is transmitted first.1 MSB is transmitted first.3FSEFrame Sync Early0 Frame sync asserts with the first bit of the frame.1 Frame sync asserts one bit before the first bit of the frame.2ONDEMOn Demand ModeTable continues on the next page...Memory map and register definitionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016798 Freescale Semiconductor, Inc.
