36.5.4.1.2 SCL high timeoutWhen the I2C module has determined that the SMBCLK and SMBDAT signals havebeen high for at least THIGH:MAX, it assumes that the bus is idle.A HIGH timeout occurs after a START condition appears on the bus but before a STOPcondition appears on the bus. Any master detecting this scenario can assume the bus isfree when either of the following occurs:• SHTF1 rises.• The BUSY bit is high and SHTF1 is high.When the SMBDAT signal is low and the SMBCLK signal is high for a period of time,another kind of timeout occurs. The time period must be defined in software. SHTF2 isused as the flag when the time limit is reached. This flag is also an interrupt resource, soit triggers IICIF.36.5.4.1.3 CSMBCLK TIMEOUT MEXT and CSMBCLK TIMEOUT SEXTThe following figure illustrates the definition of the timeout intervals TLOW:SEXT andTLOW:MEXT. When in master mode, the I2C module must not cumulatively extend itsclock cycles for a period greater than TLOW:MEXT within a byte, where each byte isdefined as START-to-ACK, ACK-to-ACK, or ACK-to-STOP. When CSMBCLKTIMEOUT MEXT occurs, SMBus MEXT rises and also triggers the SLTF.Start LOW:SEXTT StopLOW:MEXTT ClkAckLOW:MEXTT ClkAckLOW:MEXTTSCLSDAFigure 36-4. Timeout measurement intervalsA master is allowed to abort the transaction in progress to any slave that violates theTLOW:SEXT or TTIMEOUT,MIN specifications. To abort the transaction, the master issues aSTOP condition at the conclusion of the byte transfer in progress. When a slave, the I2Cmodule must not cumulatively extend its clock cycles for a period greater thanTLOW:SEXT during any message from the initial START to the STOP. When CSMBCLKTIMEOUT SEXT occurs, SEXT rises and also triggers SLTF.Functional descriptionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016636 Freescale Semiconductor, Inc.
