37.4.4.1 8-bit, 9-bit and 10-bit data modesThe LPUART transmitter and receiver can be configured to operate in 9-bit data mode bysetting the LPUART_CTRL[M] or 10-bit data mode by setting LPUART_CTRL[M10].In 9-bit mode, there is a ninth data bit in 10-bit mode there is a tenth data bit. For thetransmit data buffer, these bits are stored in LPUART_CTRL[T8] andLPUART_CTRL[T9]. For the receiver, these bits are held in LPUART_CTRL[R8] andLPUART_CTRL[R9]. They are also accessible via 16-bit or 32-bit accesses to theLPUART_DATA register.For coherent 8-bit writes to the transmit data buffer, write to LPUART_CTRL[T8] andLPUART_CTRL[T9] before writing to LPUART_DATA[7:0]. For 16-bit and 32-bitwrites to the LPUART_DATA register all 10 transmit bits are written to the transmit databuffer at the same time.If the bit values to be transmitted as the ninth and tenth bit of a new character are thesame as for the previous character, it is not necessary to write to LPUART_CTRL[T8]and LPUART_CTRL[T9] again. When data is transferred from the transmit data buffer tothe transmit shifter, the value in LPUART_CTRL[T8] and LPUART_CTRL[T9] iscopied at the same time data is transferred from LPUART_DATA[7:0] to the shifter.The 9-bit data mode is typically used with parity to allow eight bits of data plus the parityin the ninth bit, or it is used with address-mark wakeup so the ninth data bit can serve asthe wakeup bit. The 10-bit data mode is typically used with parity and address-markwakeup so the ninth data bit can serve as the wakeup bit and the tenth bit as the parity bit.In custom protocols, the ninth and/or tenth bits can also serve as software-controlledmarkers.37.4.4.2 Idle lengthAn idle character is a character where the start bit, all data bits and stop bits are in themark postion. The CTRL[ILT] register can be configured to start detecting an idlecharacter from the previous start bit (any data bits and stop bits count towards the idlecharacter detection) or from the previous stop bit.The number of idle characters that must be received before an idle line condition isdetected can also be configured using the CTRL[IDLECFG] field. This field configuresthe number of idle characters that must be received before the STAT[IDLE] flag is set,the STAT[RAF] flag is cleared and the DATA[IDLINE] flag is set with the next receivedcharacter.Functional descriptionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016674 Freescale Semiconductor, Inc.
