RECEIVERRT CLOCKMSB STOPDATASAMPLESRT16RT15RT14RT13RT12RT11RT10RT9RT8RT7RT6RT5RT4RT3RT2RT1Figure 38-10. Slow dataFor an 8-bit data character, data sampling of the stop bit takes the receiver 154 RT cycles(9 bit times × 16 RT cycles + 10 RT cycles).With the misaligned character shown in the Figure 38-10, the receiver counts 154 RTcycles at the point when the count of the transmitting device is 147 RT cycles (9 bit times× 16 RT cycles + 3 RT cycles).The maximum percent difference between the receiver count and the transmitter count ofa slow 8-bit data character with no errors is:((154 − 147) ÷ 154) × 100 = 4.54%For a 9-bit data character, data sampling of the stop bit takes the receiver 170 RT cycles(10 bit times × 16 RT cycles + 10 RT cycles).With the misaligned character shown in the Figure 38-10, the receiver counts 170 RTcycles at the point when the count of the transmitting device is 163 RT cycles (10 bittimes × 16 RT cycles + 3 RT cycles).The maximum percent difference between the receiver count and the transmitter count ofa slow 9-bit character with no errors is:((170 − 163) ÷ 170) × 100 = 4.12%38.5.2.7.2 Fast data toleranceThe following figure shows how much a fast received frame can be misaligned. The faststop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10.RECEIVERRT CLOCKSTOP IDLE OR NEXT FRAMEDATASAMPLESRT16RT15RT14RT13RT12RT11RT10RT9RT8RT7RT6RT5RT4RT3RT2RT1Figure 38-11. Fast dataChapter 38 Universal Asynchronous Receiver/Transmitter(UART)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 721
