The transmitter and receiver can independently select between the bus clock and theaudio master clock to generate the bit clock. The module's Clocking Mode field of theTransmit Configuration 2 Register and Receive Configuration 2 Register (TCR2[MSEL]and RCR2[MSEL]) selects the master clock.The following table shows the TCR2[MSEL] and RCR2[MSEL] field settings for thisdevice.Table 40-2. I2S0 master clock settingsTCR2[MSEL], RCR2[MSEL] Master Clock00 Bus Clock01 I2S0_MCLK10 Not supported11 Not supported40.1.3.5 Clock gating and I2S/SAI initializationThe clock to the I2S/SAI module can be gated using a bit in the SIM. To minimize powerconsumption, these bits are cleared after any reset, which disables the clock to thecorresponding module. The clock enable bit should be set by software at the beginning ofthe module initialization routine to enable the module clock before initialization of any ofthe I2S/SAI registers.40.1.4 I2S/SAI operation in low power modes40.1.4.1 Stop and very low power modesIn Stop mode, the SAI transmitter and/or receiver can continue operating provided theappropriate Stop Enable bit is set (TCSR[STOPE] and/or RCSR[STOPE], respectively),and provided the transmitter and/or receiver is/are using an externally generated bit clockor an Audio Master Clock that remains operating in Stop mode. The SAI transmitterand/or receiver can generate an asynchronous interrupt to wake the CPU from Stop mode.In VLPS mode, the module behaves as it does in stop mode if VLPS mode is enteredfrom run mode. However, if VLPS mode is entered from VLPR mode, the FIFO mightunderflow or overflow before wakeup from stop mode due to the limits in bus bandwidth.In VLPW and VLPR modes, the module is limited by the maximum bus clockfrequencies.Chapter 40 Synchronous Audio Interface (SAI)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 787
