xCYCLE RULERhclkBME AHB Input Busmx_haddrmx_hattrmx_hwritemx_hwdatamx_hrdatamx_hreadyBME AHB Output Bussx_haddrsx_hattrsx_hwritesx_hwdatasx_hrdatasx_hreadyBME States + Datapathcontrol_state_dp1control_state_dp2reg_addr_data_dpx+3x+2x+1nextnextnextnextnextnext5..v_wxyz5..v_wxyz wdata bfi rdatawdata bfi rdatardata400v_wxyz400v_wxyzwdataFigure 42-2. Decorated store: bit field insert timing diagramAll the decorated store operations follow the same execution template shown in Figure42-2, a two-cycle read-modify-write operation:1. Cycle x, 1st AHB address phase: Write from input bus is translated into a readoperation on the output bus using the actual memory address (with the decorationremoved) and then captured in a register.2. Cycle x+1, 2nd AHB address phase: Write access with the registered (but actual)memory address is output3. Cycle x+1, 1st AHB data phase: Memory read data is modified using the input buswrite data and the function defined by the decoration and captured in a data register;the input bus cycle is stalled.4. Cycle x+2, 2nd AHB data phase: Registered write data is sourced onto the outputwrite data bus.NOTEAny wait states inserted by the slave device are simply passedthrough the BME back to the master input bus, stalling theAHB transaction cycle for cycle.Chapter 42 Bit Manipulation Engine (BME)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 835
