The EPWM period is determined by (MOD + 0x0001) and the pulse width (duty cycle) isdetermined by CnV.The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at thechannel (n) match (TPM counter = CnV), that is, at the end of the pulse width.This type of PWM signal is called edge-aligned because the leading edges of all PWMsignals are aligned with the beginning of the period, which is the same for all channelswithin an TPM.periodcounter overflow counter overflow counter overflowchannel (n) outputchannel (n) match channel (n) match channel (n) matchpulsewidthFigure 29-9. EPWM period and pulse width with ELSnB:ELSnA = 1:0If (ELSnB:ELSnA = 0:0) when the counter reaches the value in the CnV register, theCHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1), however thechannel (n) output is not controlled by TPM.If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the counteroverflow (when the zero is loaded into the TPM counter), and it is forced low at thechannel (n) match (TPM counter = CnV) (see the following figure).TOF bitCHnF bitCNTchannel (n) outputMOD = 0x0008CnV = 0x0005counteroverflow channel (n)match counteroverflow... 0 1 2 3 4 5 6 7 8 0 1 2 ...previous valueFigure 29-10. EPWM signal with ELSnB:ELSnA = 1:0If (ELSnB:ELSnA = X:1), then the channel (n) output is forced low at the counteroverflow (when zero is loaded into the TPM counter), and it is forced high at the channel(n) match (TPM counter = CnV) (see the following figure).Chapter 29 Timer/PWM Module (TPM)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 481
