If the bus frequency is less than fADCK, precise sample time for continuous conversionscannot be guaranteed when short sample is enabled, that is, when CFG1[ADLSMP]=0.The maximum total conversion time is determined by the clock source chosen and thedivide ratio selected. The clock source is selectable by CFG1[ADICLK], and the divideratio is specified by CFG1[ADIV].The maximum total conversion time for all configurations is summarized in the equationbelow. See the following tables for the variables referenced in the equation.Equation 1. Conversion time equationTable 23-5. Single or first continuous time adder (SFCAdder)CFG1[ADLSMP]CFG2[ADACKEN] CFG1[ADICLK] Single or first continuous time adder (SFCAdder)1 x 0x, 10 3 ADCK cycles + 5 bus clock cycles1 1 11 3 ADCK cycles + 5 bus clock cycles11 0 11 5 μs + 3 ADCK cycles + 5 bus clock cycles0 x 0x, 10 5 ADCK cycles + 5 bus clock cycles0 1 11 5 ADCK cycles + 5 bus clock cycles10 0 11 5 μs + 5 ADCK cycles + 5 bus clock cycles1. To achieve this time, CFG2[ADACKEN] must be 1 for at least 5 μs prior to the conversion is initiated.Table 23-6. Average number factor (AverageNum)SC3[AVGE] SC3[AVGS] Average number factor (AverageNum)0 xx 11 00 41 01 81 10 161 11 32Table 23-7. Base conversion time (BCT)Mode Base conversion time (BCT)8b single-ended 17 ADCK cycles9b differential 27 ADCK cycles10b single-ended 20 ADCK cycles11b differential 30 ADCK cycles12b single-ended 20 ADCK cycles13b differential 30 ADCK cyclesTable continues on the next page...Functional descriptionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016370 Freescale Semiconductor, Inc.
