I2Cx_S field descriptions (continued)Field DescriptionIndicates the status of the bus regardless of slave or master mode. This bit is set when a START signal isdetected and cleared when a STOP signal is detected.0 Bus is idle1 Bus is busy4ARBLArbitration LostThis bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared bysoftware, by writing 1 to it.0 Standard bus operation.1 Loss of arbitration.3RAMRange Address MatchThis bit is set to 1 by any of the following conditions, if I2C_C2[RMEN] = 1:• Any nonzero calling address is received that matches the address in the RA register.• The calling address is within the range of values of the A1 and RA registers.NOTE: For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.Writing the C1 register with any value clears this bit to 0.0 Not addressed1 Addressed as a slave2SRWSlave Read/WriteWhen addressed as a slave, SRW indicates the value of the R/W command bit of the calling address sentto the master.0 Slave receive, master writing to slave1 Slave transmit, master reading from slave1IICIFInterrupt FlagThis bit sets when an interrupt is pending. This bit must be cleared by software by writing 1 to it, such as inthe interrupt routine. One of the following events can set this bit:• One byte transfer, including ACK/NACK bit, completes if FACK is 0. An ACK or NACK is sent on thebus by writing 0 or 1 to TXAK after this bit is set in receive mode.• One byte transfer, excluding ACK/NACK bit, completes if FACK is 1.• Match of slave address to calling address including primary slave address, range slave address,alert response address, second slave address, or general call address.• Arbitration lost• In SMBus mode, any timeouts except SCL and SDA high timeouts• I2C bus stop or start detection if the SSIE bit in the Input Glitch Filter register is 1NOTE: To clear the I2C bus stop or start detection interrupt: In the interrupt serviceroutine, first clear the STOPF or STARTF bit in the Input Glitch Filter register bywriting 1 to it, and then clear the IICIF bit. If this sequence is reversed, the IICIFbit is asserted again.0 No interrupt pending1 Interrupt pending0RXAKReceive AcknowledgeTable continues on the next page...Chapter 36 Inter-Integrated Circuit (I2C)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 619
