I2Sx_RCR2 field descriptions (continued)Field Description0 Use the normal bit clock source.1 Swap the bit clock source.28BCIBit Clock InputWhen this field is set and using an internally generated bit clock in either synchronous or asynchronousmode, the bit clock actually used by the receiver is delayed by the pad output delay (the receiver isclocked by the pad input as if the clock was externally generated). This has the effect of decreasing thedata input setup time, but increasing the data output valid time.The slave mode timing from the datasheet should be used for the receiver when this bit is set. Insynchronous mode, this bit allows the receiver to use the slave mode timing from the datasheet, while thetransmitter uses the master mode timing. This field has no effect when configured for an externallygenerated bit clock .0 No effect.1 Internal logic is clocked as if bit clock was externally generated.27–26MSELMCLK SelectSelects the audio Master Clock option used to generate an internally generated bit clock. This field has noeffect when configured for an externally generated bit clock.NOTE: Depending on the device, some Master Clock options might not be available. See the chip-specific information for the availability and chip-specific meaning of each option.00 Bus Clock selected.01 Master Clock (MCLK) 1 option selected.10 Master Clock (MCLK) 2 option selected.11 Master Clock (MCLK) 3 option selected.25BCPBit Clock PolarityConfigures the polarity of the bit clock.0 Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.1 Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.24BCDBit Clock DirectionConfigures the direction of the bit clock.0 Bit clock is generated externally in Slave mode.1 Bit clock is generated internally in Master mode.23–8ReservedThis field is reserved.This read-only field is reserved and always has the value 0.DIV Bit Clock DivideDivides down the audio master clock to generate the bit clock when configured for an internal bit clock.The division value is (DIV + 1) * 2.Chapter 40 Synchronous Audio Interface (SAI)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 805
