When a program detects that the receive data register is full (LPUART_STAT[RDRF] =1), it gets the data from the receive data register by reading LPUART_DATA. Refer toInterrupts and status flags for details about flag clearing.37.4.3.1 Data sampling techniqueThe LPUART receiver supports a configurable oversampling rate of between 4× and 32×of the baud rate clock for sampling. The receiver starts by taking logic level samples atthe oversampling rate times the baud rate to search for a falling edge on theLPUART_RX serial data input pin. A falling edge is defined as a logic 0 sample afterthree consecutive logic 1 samples. The oversampling baud rate clock divides the bit timeinto 4 to 32 segments from 1 to OSR (where OSR is the configured oversampling ratio).When a falling edge is located, three more samples are taken at (OSR/2), (OSR/2)+1, and(OSR/2)+2 to make sure this was a real start bit and not merely noise. If at least two ofthese three samples are 0, the receiver assumes it is synchronized to a received character.If another falling edge is detected before the receiver is considered synchronized, thereceiver restarts the sampling from the first segment.The receiver then samples each bit time, including the start and stop bits, at (OSR/2),(OSR/2)+1, and (OSR/2)+2 to determine the logic level for that bit. The logic level isinterpreted to be that of the majority of the samples taken during the bit time. If anysample in any bit time, including the start and stop bits, in a character frame fails to agreewith the logic level for that bit, the noise flag (LPUART_STAT[NF]) is set when thereceived character is transferred to the receive data buffer.When the LPUART receiver is configured to sample on both edges of the baud rateclock, the number of segments in each received bit is effectively doubled (from 1 toOSR×2). The start and data bits are then sampled at OSR, OSR+1 and OSR+2. Samplingon both edges of the clock must be enabled for oversampling rates of 4× to 7× and isoptional for higher oversampling rates.The falling edge detection logic continuously looks for falling edges. If an edge isdetected, the sample clock is resynchronized to bit times (unless resynchronization hasbeen disabled). This improves the reliability of the receiver in the presence of noise ormismatched baud rates. It does not improve worst case analysis because some charactersdo not have any extra falling edges anywhere in the character frame.In the case of a framing error, provided the received character was not a break character,the sampling logic that searches for a falling edge is filled with three logic 1 samples sothat a new start bit can be detected almost immediately.Chapter 37 Low Power Universal asynchronous receiver/transmitter (LPUART)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 669
