The Shifter Status Flag (SHIFTSTAT[SSF]) and any enabled interrupts or DMA requestswill set when data has been loaded from the SHIFTBUF register into the Shifter or whenthe Shifter is initially configured into Transmit mode. The flag will clear when new datahas been written into the SHIFTBUF register.The Shifter Error Flag (SHIFTERR[SEF]) and any enabled interrupts will set when anattempt to load data from an empty SHIFTBUF register occurs (buffer underrun). Theflag can be cleared by writing it with logic 1.39.4.1.2 Receive ModeWhen configured for Receive mode (SHIFTCTL[SMOD]=Receive), the shifter will shiftdata in and store data into the SHIFTBUF register when a store event is signalled by theassigned Timer. Checking for a start/stop bit can be enabled before/after shifter data issampled by configuring the SHIFTCFG[SSTART], TIMCFG[TSTART] orSHIFTCFG[SSTOP], TIMCFG[TSTOP] registers in the Shifter and Timer.The Shifter Status Flag (SHIFTSTAT[SSF]) and any enabled interrupts or DMA requestswill set when data has been stored into the SHIFTBUF register from the Shifter. The flagwill clear when the data has been read from the SHIFTBUF register.The Shifter Error Flag (SHIFTERR[SEF]) and any enabled interrupts will set when anattempt to store data into a full SHIFTBUF register occurs (buffer overrun) or when amismatch occurs on a start/stop bit check. The flag can be cleared by writing it with logic1.39.4.1.3 Match Store ModeWhen configured for Match Store mode (SHIFTCTL[SMOD]=Match Store), the shifterwill shift data in, check for a match result and store matched data into the SHIFTBUFregister when a store event is signalled by the assigned Timer. Checking for a start/stopbit can be enabled before/after shifter data is sampled by configuring theSHIFTCFG[SSTART], TIMCFG[TSTART] or SHIFTCFG[SSTOP], TIMCFG[TSTOP]registers in the Shifter and Timer. Up to 16-bits of data can be compared usingSHIFTBUF[31:16] to configure the data to be matched and SHIFTBUF[15:0] to mask thematch result.The Shifter Status Flag (SHIFTSTAT[SSF]) and any enabled interrupts or DMA requestswill set when a match occurs and matched data has been stored into the SHIFTBUFregister from the Shifter. The flag will clear when the matched data has been read fromthe SHIFTBUF register.Functional descriptionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016768 Freescale Semiconductor, Inc.
