SPIx_S field descriptions (continued)Field Description0 SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (whenFIFOMODE is 1)1 SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (whenFIFOMODE is 1)4MODFMaster Mode Fault FlagMODF is set if the SPI is configured as a master and the slave select input goes low, indicating someother SPI device is also configured as a master. The SS pin acts as a mode fault error input only whenC1[MSTR] is 1, C2[MODFEN] is 1, and C1[SSOE] is 0; otherwise, MODF will never be set. MODF iscleared by reading MODF while it is 1 and then writing to the SPI Control Register 1 (C1).0 No mode fault error1 Mode fault error detected3RNFULLFReceive FIFO nearly full flagThis flag is set when more than three 16-bit words or six 8-bit bytes of data remain in the receive FIFO,provided C3[RNFULLF_MARK] is 0, or when more than two 16-bit words or four 8-bit bytes of data remainin the receive FIFO, provided C3[RNFULLF_MARK] is 1. It has no function if FIFOMODE is not present oris 0.0 Receive FIFO has received less than 48 bits (when C3[RNFULLF_MARK] is 0) or less than 32 bits(when C3[RNFULLF_MARK] is 1)1 Receive FIFO has received data of an amount equal to or greater than 48 bits (whenC3[RNFULLF_MARK] is 0) or 32 bits (when C3[RNFULLF_MARK] is 1)2TNEAREFTransmit FIFO nearly empty flagThis flag is set when only one 16-bit word or two 8-bit bytes of data remain in the transmit FIFO, providedC3[TNEAREF_MARK] is 0, or when only two 16-bit words or four 8-bit bytes of data remain in the transmitFIFO, provided C3[TNEAREF_MARK] is 1. If FIFOMODE is not enabled, ignore this bit.NOTE: At an initial POR, the values of TNEAREF and RFIFOEF are 0. However, the status (S) registerand both TX and RX FIFOs are reset due to a change of SPIMODE, FIFOMODE or SPE. If thistype of reset occurs and FIFOMODE is 0, TNEAREF and RFIFOEF continue to reset to 0. If thistype of reset occurs and FIFOMODE is 1, TNEAREF and RFIFOEF reset to 1.0 Transmit FIFO has more than 16 bits (when C3[TNEAREF_MARK] is 0) or more than 32 bits (whenC3[TNEAREF_MARK] is 1) remaining to transmit1 Transmit FIFO has an amount of data equal to or less than 16 bits (when C3[TNEAREF_MARK] is 0)or 32 bits (when C3[TNEAREF_MARK] is 1) remaining to transmit1TXFULLFTransmit FIFO full flagThis bit indicates the status of the transmit FIFO when FIFOMODE is enabled. This flag is set when thereare 8 bytes in the transmit FIFO. If FIFOMODE is not enabled, ignore this bit.When FIFOMODE and DMA are both enabled, the inverted TXFULLF is used to trigger a DMA transfer.So when the transmit FIFO is not full, the DMA request is active, and remains active until the FIFO is full.0 Transmit FIFO has less than 8 bytes1 Transmit FIFO has 8 bytes of data0RFIFOEFSPI read FIFO empty flagThis bit indicates the status of the read FIFO when FIFOMODE is enabled. If FIFOMODE is not enabled,ignore this bit.Table continues on the next page...Chapter 35 Serial Peripheral Interface (SPI)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 577
