If no new character is waiting in the transmit data buffer after a stop bit is shifted out theLPUART_TX pin, the transmitter sets the transmit complete flag and enters an idlemode, with LPUART_TX high, waiting for more characters to transmit.Writing 0 to CTRL[TE] does not immediately disable the transmitter. The currenttransmit activity in progress must first be completed (that could include a data character,idle character or break character), although the transmitter will not start transmittinganother character.37.4.2.1 Send break and queued idleThe LPUART_CTRL[SBK] bit sends break characters originally used to gain theattention of old teletype receivers. Break characters are a full character time of logic 0,10-bit to 12-bit times including the start and stop bits. A longer break of 13-bit times canbe enabled by setting LPUART_STAT[BRK13]. Normally, a program would wait forLPUART_STAT[TDRE] to become set to indicate the last character of a message hasmoved to the transmit shifter, write 1, and then write 0 to the LPUART_CTRL[SBK] bit.This action queues a break character to be sent as soon as the shifter is available. IfLPUART_CTRL[SBK] remains 1 when the queued break moves into the shifter,synchronized to the baud rate clock, an additional break character is queued. If thereceiving device is another Freescale Semiconductor LPUART, the break characters arereceived as 0s in all data bits and a framing error (LPUART_STAT[FE] = 1) occurs.A break character can also be transmitted by writing to the LPUART_DATA registerwith bit 13 set and the data bits clear. This supports transmitting the break character aspart of the normal data stream and also allows the DMA to transmit a break character.When idle-line wakeup is used, a full character time of idle (logic 1) is needed betweenmessages to wake up any sleeping receivers. Normally, a program would wait forLPUART_STAT[TDRE] to become set to indicate the last character of a message hasmoved to the transmit shifter, then write 0 and then write 1 to the LPUART_CTRL[TE]bit. This action queues an idle character to be sent as soon as the shifter is available. Aslong as the character in the shifter does not finish while LPUART_CTRL[TE] is cleared,the LPUART transmitter never actually releases control of the LPUART_TX pin.An idle character can also be transmitted by writing to the LPUART_DATA register withbit 13 set and the data bits also set. This supports transmitting the idle character as part ofthe normal data stream and also allows the DMA to transmit a break character.The length of the break character is affected by the LPUART_STAT[BRK13],LPUART_CTRL[M], LPUART_BAUD[M10] and LPUART_BAUD[SNBS] bits asshown below.Chapter 37 Low Power Universal asynchronous receiver/transmitter (LPUART)KL27 Sub-Family Reference Manual , Rev. 5, 01/2016Freescale Semiconductor, Inc. 667
