The conversion time for a single conversion is calculated by using the Equation 1 on page370, and the information provided in Table 23-5 through Table 23-9. The table belowlists the variables of Equation 1 on page 370.Table 23-10. Typical conversion timeVariable TimeSFCAdder 5 ADCK cycles + 5 bus clock cyclesAverageNum 1BCT 20 ADCK cyclesLSTAdder 0HSCAdder 0The resulting conversion time is generated using the parameters listed in the precedingtable. Therefore, for a bus clock and an ADCK frequency equal to 8 MHz, the resultingconversion time is 3.75 μs.23.5.4.6.2 Long conversion time configurationA configuration for long ADC conversion is:• 16-bit differential mode with the bus clock selected as the input clock source• The input clock divide-by-8 ratio selected• Bus frequency of 8 MHz• Long sample time enabled• Configured for longest adder• High-speed conversion disabled• Average enabled for 32 conversionsThe conversion time for this conversion is calculated by using the Equation 1 on page370, and the information provided in Table 23-5 through Table 23-9. The following tablelists the variables of the Equation 1 on page 370.Table 23-11. Typical conversion timeVariable TimeSFCAdder 3 ADCK cycles + 5 bus clock cyclesAverageNum 32BCT 34 ADCK cyclesLSTAdder 20 ADCK cyclesHSCAdder 0Functional descriptionKL27 Sub-Family Reference Manual , Rev. 5, 01/2016372 Freescale Semiconductor, Inc.
