NXP Semiconductors LPC43 Series User Manual

Contents

NXP Semiconductors LPC43 Series User Manual Manual pdf 1007 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 1007 of 1269NXP Semiconductors UM10503Chapter 39: LPC43xx SSP0/139.6.4 SSP Status RegisterThis read-only register reflects the current status of the SSP controller.39.6.5 SSP Clock Prescale RegisterThis register controls the factor by which the Prescaler divides the SSP peripheral clockPCLK to yield the prescaler clock that is, in turn, divided by the SCR factor in SSPnCR0,to determine the bit clock.Important: the SSPnCPSR value must be properly initialized or the SSP controller will notbe able to transmit data correctly.In Slave mode, the SSP clock rate provided by the master must not exceed 1/12 of theSSP peripheral clock. The content of the SSPnCPSR register is not relevant.In master mode, CPSDVSR min = 2 or larger (even numbers only).39.6.6 SSP Interrupt Mask Set/Clear RegisterThis register controls whether each of the four possible interrupt conditions in the SSPcontroller are enabled. Note that ARM uses the word “masked” in the opposite sense fromclassic computer terminology, in which “masked” meant “disabled”. ARM uses the word“masked” to mean “enabled”. To avoid confusion we will not use the word “masked”.Table 876: SSP Status Register (SR - address 0x4008 300C (SSP0), 0x400C 500C (SSP1)) bitdescriptionBit Symbol Description Resetvalue0 TFE Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. 11 TNF Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 12 RNE Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 ifnot.03 RFF Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. 04 BSY Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currentlysending/receiving a frame and/or the Tx FIFO is not empty.031:5 - Reserved, user software should not write ones to reserved bits. Thevalue read from a reserved bit is not defined.NATable 877: SSP Clock Prescale Register (CPSR - address 0x4008 3010 (SSP0), 0x400C 5010(SSP1)) bit descriptionBit Symbol Description Resetvalue7:0 CPSDVSR This even value between 2 and 254, by which PCLK is divided to yieldthe prescaler output clock. Bit 0 always reads as 0.031:8 - Reserved, user software should not write ones to reserved bits. Thevalue read from a reserved bit is not defined.NA