NXP Semiconductors LPC43 Series User Manual

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NXP Semiconductors LPC43 Series User Manual Manual pdf 740 page image

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.User manual Rev. 1.3 — 6 July 2012 740 of 1269NXP Semiconductors UM10503Chapter 26: LPC43xx EthernetExample: Buffer writeIf the Receive buffer address is 0x0000FF2 (for 64-bit data bus) and 16 bytes of areceived frame need to be transferred, then the DMA writes 3 full words from address0x00000FF0. But the first 2 bytes of first transfer and the last 6 bytes of the third transferhave dummy data.26.7.5.1.3 Buffer size calculationsThe DMA does not update the size fields in the Transmit and Receive descriptors. TheDMA updates only the status fields (RDES and TDES) of the descriptors. The driver hasto perform the size calculations.The transmit DMA transfers the exact number of bytes (indicated by buffer size field ofTDES1) towards the MAC core. If a descriptor is marked as first (FS bit of TDES1 is set),then the DMA marks the first transfer from the buffer as the start of frame. If a descriptor ismarked as last (LS bit of TDES1), then the DMA marks the last transfer from that databuffer as the end-of frame to the MTL.The Receive DMA transfers data to a buffer until the buffer is full or the end-of frame isreceived from the MTL. If a descriptor is not marked as last (LS bit of RDES0), then thedescriptor’s corresponding buffer(s) are full and the amount of valid data in a buffer isaccurately indicated by its buffer size field minus the data buffer pointer offset when theFS bit of that descriptor is set. The offset is zero when the data buffer pointer is aligned tothe data bus width. If a descriptor is marked as last, then the buffer may not be full (asindicated by the buffer size in RDES1). To compute the amount of valid data in this finalbuffer, the driver must read the frame length (FL bits of RDES0[29:16]) and subtract thesum of the buffer sizes of the preceding buffers in this frame. The Receive DMA alwaystransfers the start of next frame with a new descriptor.Remark: Even when the start address of a receive buffer is not aligned to the systembus’s data width, the system should allocate a receive buffer of a size aligned to thesystem bus width. For example, if the system allocates a 1,024-byte (1 KB) receive bufferstarting from address 0x1000, the software can program the buffer start address in theReceive descriptor to have a 0x1002 offset. The Receive DMA writes the frame to thisbuffer with dummy data in the first two locations (0x1000 and 0x1001). The actual frame iswritten from location 0x1002. Thus, the actual useful space in this buffer is 1,022 bytes,even though the buffer size is programmed as 1,024 bytes, because of the start addressoffset.26.7.5.1.4 DMA arbiterThe arbiter inside the DMA module performs the arbitration between the Transmit andReceive channel accesses to the AHB Master interface. Two types of arbitrations arepossible: round-robin, and fixed-priority.When round-robin arbitration is selected (DA bit of Register Table 560 (Bus ModeRegister) is reset), the arbiter allocates the data bus in the ratio set by the PR bits of DMARegister Table 560, when both Transmit and Receive DMAs are requesting for accesssimultaneously. When the DA bit is set, the Receive DMA always gets priority over theTransmit DMA for data access by default. When the TXPR bit (bit 27 of DMA registerTable 560) is also set, then the Transmit DMA gets priority over the Receive DMA.